Method of forming active and isolation areas with split active patterning

ABSTRACT

A process for forming isolation and active regions, wherein the patterning of an oxidation-barrier active stack is performed separately in the PMOS and NMOS regions. After the active stack is in place, two masking steps are used: one exposes the isolation areas on the NMOS side, for stack etch, channel-stop implant, and silicon recess etch (optional). The other masking step is exactly complementary, and performs the analogous operations on the PMOS side. After these two steps are performed (in either order), an additional nitride layer can optionally be deposited and etched to cover the sidewall of the active stack. Field oxide is then formed, and processing then proceeds in conventional fashion.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to integrated circuit isolation structures.

[0002] Background: Isolation Technologies

[0003] Adjacent elements on an integrated circuit must be electrically isolated from each other if they are to function independently. Therefore, it has long been recognized that the most basic elements of integrated circuit technology include not only active devices and interconnect, but also isolation.

[0004] The standard industry process for isolation of CMOS circuits has long been LOCOS (“LOCal Oxidation of Silicon”). In this process, a stack of silicon nitride and silicon oxide layers (or a stack of silicon nitride, polysilicon and oxide layers), is patterned to provide an oxidation barrier in locations where active devices are to be formed (i.e., the active regions). This stack is referred to as an “active stack.” Silicon is exposed in locations where a field oxide is desired for isolation. A “channel-stop” implant is then performed, using dopants which will prevent parasitic transistors from turning on. In CMOS processes (including BiCMOS, CBCMOS, etc.), two channel-stop implants are often necessary, one for P-type regions and one for N-type regions. Thus, two mask steps (in addition to the active mask) are normally required.¹

[0005] The wafer is then placed in an oxidizing environment to grow a thick field oxide (typically at least several thousand Ångstroms)² on the exposed silicon areas. Silicon under the nitride will generally not be oxidized EXCEPT at the edge of the active stack, where lateral diffusion of oxygen under the active stack will cause a tapered shape, known as a “bird's beak,” in the resulting structure.

[0006] Background: Alternatives to LOCOS

[0007] A problem with LOCOS is that the bird's beak costs a substantial amount of area. For many years there have therefore been substantial attempts to find an alternative to LOCOS. Many of the proposed alternative technologies also use localized oxidation, with modifications to reduce the width of the bird's beak.³

[0008] Other approaches use additional nitride to provide some lateral barrier to encroachment during the oxide growth step. See Kurosawa et al., “A New Bird's-Beak Free Field Isolation Technology for VLSI Devices,” 1981 IEDM 384ff, which is hereby incorporated by reference (“BOX” isolation or “Buried OXide isolation”); Chiu et al., “The SWAMI—A Defect Free and Near-Zero Bird's-Beak Local Oxidation Process and Its Application in VLSI Technology,” 1982 IEDM 224ff, which is hereby incorporated by reference (“SWAMI” or “SideWAll Masked Isolation”); Hui et al., “Electrical Properties of MOS Devices Made With SILO Technology,” 1982 IEDM 220ff, which is hereby incorporated by reference (“SILO” or “Sealed Interface Local Oxidation”).

[0009] Difficulties of Conventional Mask Allocation

[0010] All conventional isolation process using localized oxidation have the following drawbacks as applied to modern technology:

[0011] 1. If both n and p channel stop implants must be performed, then 3 masks will be needed: one for active, one for NMOS channel stop, and one for PMOS channel stop. Counterdoping may be able to eliminate one of these masks, but counterdoping imposes its own constraints.

[0012] 2. The critical dimension (CD), or minimum geometry, cannot be optimized for the active areas in both N-well and P-well regions, due to the depth difference caused by typical well formation processes.

[0013] 3. Unless the active stack is capable of blocking the channel stop implants, the photoresist on top of active stack must be hardened after active etch to survive the channel stop implant patterning to block the dopant. Critical dimension and slope of the photoresist must be sacrificed in order for the photoresist to survive second patterning. Channel stop patterning is also affected by the first layer of photoresist.

SUMMARY OF THE INVENTION

[0014] The present invention provides a new technique for forming active and isolation areas, wherein the active areas in p regions and n regions are etched separately, using two separate patterning steps. Each of these two patterning steps not only patterns the oxidation barrier, but also patterns the respective channel stop implant (and optionally also a silicon recess etch).

[0015] Advantages of the new process include (but are not limited to) the following:

[0016] 1. Two masks are needed instead of the three which would otherwise be required (unless counterdoping were used) if both n-type and p-type channel stop implants must be performed.

[0017] 2. The critical dimensions of the active areas can be optimized separately in the n and p regions.

[0018] 3. Even if the active stack is incapable of blocking channel stop implant, it is not necessary to pattern photoresist on top of photoresist. In fact, with the disclosed innovative process, the active stack's power of blocking implant dopant is no longer a factor in choosing the active stack. Thus, higher energies can be used for the channel-stop implant if desired, without the difficulties of photoresis-on-photoresist processing.

[0019] 4. The depth of recess etching into silicon in n and p regions can be independently adjusted to achieve the best planarization.

[0020] It should also be noted that the two needed masks can be expressed as logical combinations of an “active” pattern with an N+ pattern and a P+ pattern, respectively. Thus the masks needed for using the present invention, while different from the conventional masks, can readily be generated for all existing layouts.

BRIEF DESCRIPTION OF THE DRAWING

[0021] The present invention will be described with reference to the accompanying drawings, which show important sample embodiments of the invention and which are incorporated in the specification hereof by reference, wherein:

[0022]FIG. 1 shows a cross-sectional view of a silicon wafer during the p channel stop implant, in a sample embodiment of the invention. (The dotted lines show the surface of silicon in an alternative embodiment, where the silicon has been recess etched.)

[0023]FIG. 2 shows a cross-sectional view of a silicon wafer during the n channel stop implant, in a sample embodiment of the invention. (The dotted lines show the surface of silicon in an alternative embodiment, where the silicon has been recess etched.)

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The numerous innovative teachings of the present application will be described with particular reference to the presently preferred embodiment. However, it should be understood that this class of embodiments provides only a few examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily delimit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others.

[0025] An example of the disclosed innovative process is as follows. (These steps are performed on a conventional silicon substrate, after the N-wells and/or P-wells have been conventionally formed to define n-type regions 102 and p-type regions 104.) 1. Deposit/grow active stack 110 (e.g. 800Å of nitride over 130Å of pad oxide). 2. Deposit and pattern photoresist 120A to expose the active stack 110 over the isolation areas 130A in the n-type regions 102. (The active areas in the n-type region, and the whole p-type region, remain covered with photoresist.)

[0026] 3. Etch the exposed portions of the active stack 110, to expose silicon in the isolation areas in the n-type region. 4. [optional] Recess etch silicon 102 if so desired, e.g. to a depth of 2000Å.

[0027] 5. Perform PMOS channel stop implant 150A (e.g. 3×10¹² cm⁻² of phosphorus at 60 keV).

[0028] (FIG. 1 shows a cross sectional view of the wafer at this stage of the process.)

[0029] 6. Remove photoresist 120A and clean wafer.

[0030] 7. Deposit and pattern photoresist 120B to expose the active stack over the isolation areas 130B in the p-type region. (The active areas 140 in the p-type region 104, and the whole n-type region 102, remain covered with photoresist 120B.)

[0031] 8. Etch the exposed portions of the active stack 110, to expose silicon 104 in the isolation areas 130Bhe p-type region 104

[0032] 9. [optional] Recess etch silicon 104 if so desired, e.g. to a depth of 2000Å.

[0033] 10. Perform NMOS channel stop implant 150B (e.g. 2.5×10¹³ cm⁻² of Boron at 100 keV).

[0034] (FIG. 2 shows a cross-sectional view of the wafer at this stage of the process.)

[0035] 11. Remove all photoresist and clean wafer.

[0036] 12. [optional] If desired, after recess etch, deposit nitride overall and perform anisotropic etchback, to form nitride sidewall on active stack 110, to reduce lateral encroachment during field oxide growth.

[0037] 13. Grow field oxide (e.g. to 5000Å) and remove active stack.

[0038] This finishes the active/isolation formation process. Processing can then continue with conventional further steps to form active devices, contacts, and interconnects.

[0039] Note that steps 7 through 11 can be performed before steps 2 through 6, if desired.

[0040] The steps of etching the active stack 110 and silicon 102/104 are preferably performed with conventional anisotropic plasma or RIE etching. As will be readily recognized by those skilled in the art, the particular process recipes and etch chemistries used for etching the active stack would be adjusted for the particular stack composition used. (For example, if the active stack includes an intermediate layer of polysilicon, then at least part of the active stack etch of step 3 should not be highly selective to silicon. For another example, if optional steps 4 and 9 are used, then a single etch step can be used to perform steps 3 and 4 together, using appropriate modulation of etchant species or using a nonselective anisotropic etch. For another example, of course the etches used do not have to 100% anisotropic, i.e. do not strictly have to achieve 100% vertical sidewalls.) In any case, the particular chemistries used are not particularly relevant to the present invention.

[0041] Further Modifications and Variations

[0042] It will be recognized by those skilled in the art that the innovative concepts disclosed in the present application can be applied in a wide variety of contexts. Moreover, the preferred implementation can be modified in a tremendous variety of ways. Accordingly, it should be understood that the modifications and variations suggested below and above are merely illustrative. These examples may help to show some of the scope of the inventive concepts, but these examples do not nearly exhaust the full scope of variations in the disclosed novel concepts.

[0043] For example, the presently preferred embodiment has been described in the context of a LOCOS process. However, the innovative ideas can also be combined with various approaches using sidewall nitride on the active stack, as discussed above. The innovative ideas can also be adapted, if desired, for combination with the various modified-LOCOS processes which have been proposed,

[0044] As will be recognized by those skilled in the art, the innovative concepts described in the present application can be modified and varied over a tremendous range of applications, and accordingly the scope of patented subject matter is not limited by any of the specific exemplary teachings given. 

What is claimed is:
 1. A fabrication method, comprising the steps of: (a) providing a substrate which includes at least one substantially monolithic body of semiconductor material; (b) forming n-type and p-type regions at a surface of said body; (c) forming an oxidation barrier layer on said surface; (d) forming a first patterned layer which exposes predetermined locations of isolation areas in said n-type region, and which covers substantially all of said p-type regions and predetermined locations of active device areas in said n-type regions; and thereafter (d.1) etching away said oxidation barrier layer where exposed by said respective patterned layer, and (d.2) implanting a first channel-stop dopant into areas exposed by said respective patterned layer, and (d.3) removing said respective patterned layer; (e) forming a second patterned layer which exposes predetermined locations of isolation areas in said p-type region, and which covers substantially all of said n-type regions and predetermined locations of active device areas in said p-type regions; and thereafter (e.1) etching away said oxidation barrier layer where exposed by said respective patterned layer, and (e.2) implanting a second channel-stop dopant into areas exposed by said respective patterned layer, and (e.3) removing said respective patterned layer; and (f) growing a field oxide on said body where exposed by said oxidation barrier layer.
 2. The method of claim 1, wherein said step (e) is performed before said step (d).
 3. The method of claim 1, wherein said step (d) is performed before said step (e).
 4. The method of claim 1, wherein said body consists of silicon.
 5. The method of claim 1, wherein said first channel-stop dopant consists of phosphorus.
 6. The method of claim 1, wherein said second channel-stop dopant consists of boron.
 7. The method of claim 1, wherein said oxidation barrier layer comprises a layer of silicon nitride overlying a layer of silicon dioxide.
 8. The method of claim 1, wherein said oxidation barrier layer comprises a silicon oxide layer, a polycrystaline silicon layer thereover, and a layer of silicon nitride thereover.
 9. The method of claim 1, wherein said oxidation barrier layer comprises a first layer of silicon nitride overlying a silicon oxide layer which overlies a second silicon nitride layer.
 10. The method of claim 1, further comprising the subsequent steps of forming active devices in at least some ones of said active areas, and forming interconnections to link said active devices in a predetermined circuit configuration.
 11. A fabrication method, comprising the steps of: (a) providing a substrate which includes at least one substantially monolithic body of semiconductor material; (b) forming n-type and p-type regions at a surface of said body; (c) forming an oxidation barrier layer on said surface; (d) forming a first patterned layer which exposes predetermined locations of isolation areas in said n-type region, and which covers substantially all of said p-type regions and predetermined locations of active device areas in said n-type regions; and thereafter (d.1A) etching away said oxidation barrier layer where exposed by said respective patterned layer, and (d.1B) etching away said body where exposed by said oxidation barrier layer, and (d.2) implanting a first channel-stop dopant into exposed areas of said body, and (d.3) removing said respective patterned layer; (e) forming a second patterned layer which exposes predetermined locations of isolation areas in said p-type region, and which covers substantially all of said n-type regions and predetermined locations of active device areas in said p-type regions; and thereafter (e.1A) etching away said oxidation barrier layer where exposed by said respective patterned layer, and (e.1B) etching away said body where exposed by said oxidation barrier layer, and (e.2) implanting a second channel-stop dopant into exposed areas of said body, and (e.3) removing said respective patterned layer; and (f) growing a field oxide on said body where exposed by said oxidation barrier layer.
 12. The method of claim 11, wherein said step (e) is performed before said step (d).
 13. The method of claim 11, wherein said step (d) is performed before said step (e).
 14. The method of claim 11, wherein said body consists of silicon.
 15. The method of claim 11, wherein said first channel-stop dopant consists of phosphorus.
 16. The method of claim 11, wherein said second channel-stop dopant consists of boron.
 17. The method of claim 11, wherein said oxidation barrier layer comprises a layer of silicon nitride overlying a layer of silicon dioxide.
 18. The method of claim 11, wherein said oxidation barrier layer comprises a silicon oxide layer, a polycrystaline silicon layer thereover, and a layer of silicon nitride thereover.
 19. The method of claim 11, wherein said oxidation barrier layer comprises a first layer of silicon nitride overlying a silicon oxide layer which overlies a second silicon nitride layer.
 20. The method of claim 11, further comprising the subsequent steps of forming active devices in at least some ones of said active areas, and forming interconnections to link said active devices in a predetermined circuit configuration.
 21. A method, comprising the steps of: (a) providing a substrate which includes at least one substantially monolithic body of semiconductor material; (b) forming n-type and p-type regions at a surface of said body; (c) forming an oxidation barrier layer on said surface; (d) forming a first patterned layer which exposes predetermined locations of isolation areas in said n-type region, and which covers substantially all of said p-type regions and predetermined locations of active device areas in said n-type regions; and thereafter (d.1) etching away said oxidation barrier layer where exposed by said respective patterned layer, and (d.2) implanting a first channel-stop dopant into areas exposed by said respective patterned layer, and (d.3) removing said respective patterned layer; (e) forming a second patterned layer which exposes predetermined locations of isolation areas in said p-type region, and which covers substantially all of said n-type regions and predetermined locations of active device areas in said p-type regions; and thereafter (e.1) etching away said oxidation barrier layer where exposed by said respective patterned layer, and (e.2) implanting a second channel-stop dopant into areas exposed by said respective patterned layer, and (e.3) removing said respective patterned layer; and (f.1) depositing and partially removing an additional layer of oxidation-resistant material; and (f.2) growing a field oxide on said body where exposed by said oxidation barrier layer.
 22. The method of claim 21, wherein said step (e) is performed before said step (d).
 23. The method of claim 21, wherein said step (d) is performed before said step (e).
 24. The method of claim 21, wherein said body consists of silicon.
 25. The method of claim 21, wherein said first channel-stop dopant consists of phosphorus.
 26. The method of claim 21, wherein said second channel-stop dopant consists of boron.
 27. The method of claim 21, wherein said oxidation barrier layer comprises a layer of silicon nitride overlying a layer of silicon dioxide.
 28. The method of claim 21, wherein said oxidation barrier layer comprises a silicon oxide layer, a polycrystaline silicon layer thereover, and a layer of silicon nitride thereover.
 29. The method of claim 21, wherein said additional oxidation-resistant material consists of silicon nitride.
 30. The method of claim 21, wherein said oxidation barrier layer comprises a first layer of silicon nitride overlying a silicon oxide layer which overlies a second silicon nitride layer.
 31. The method of claim 21, further comprising the subsequent steps of forming active devices in at least some ones of said active areas, and forming interconnections to link said active devices in a predetermined circuit configuration. 